1. Field of the Invention
The present invention relates to integrated circuit type devices generally and more particularly to a bidirectional FIFO buffer having means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion.
2. Description of the Related Art
A FIFO (first-in-first-out) buffer functions as a shift register having an additional control section that permits input data to "fall through" to the first vacant stage. In other words, if there is data stored in the FIFO buffer, it is available at the output even though all of the stages are not filled. Thus, in effect, a FIFO buffer functions as a "variable-length" shift register, the length of which is always the same as the data stored therein. (Although shift registers may be used, of late, many FIFO buffers are implemented with random access memories (RAMs) and counters.) For additional information regarding FIFO buffers, the reader is referred to my U.S. Pat. No. 4,750,149.
As such, FIFO buffers are particularly suited for use in applications in which there is a need to compensate for differences in the rate of flow of data. For example, FIFO buffers are particularly suited for use in storing data which is to be written onto a disk and/or which has been read off of a disk; for use in storing data which is to be transmitted to a local area network (LAN) and/or which has been received from a LAN; and for use in storing data which is to be printed.
Heretofore, no doubt due to the predominance of eight-bit microprocessors and/or eight-bit peripherals, most FIFO buffers have been designed with an eight-bit word length (to store eight bits of data at a time.) Of late, however, sixteen-bit and thirty-two-bit microprocessors have been gaining in popularity. Although many sixteen-bit and thirty-two-bit microprocessors have means for communicating with eight-bit peripherals (and FIFO buffers), such communication is, usually, less efficient than communication with sixteen-bit and/or thirty-two-bit peripherals. Thus, a need exists for FIFO buffers which have means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion.
Also, since data may be corrupted when transmitted over a LAN, a need exists for FIFO buffers which have means for re-reading (for re-transmission) data stored in the buffer and/or re-writing (over-writing) data stored in the buffer (with re-transmitted data).
In addition, a need exists for FIFO buffers suitable for interfacing sixteen-bit and thirty-two-bit microprocessors with eight-bit microprocessors, non-direct memory access (DMA) type peripheral devices, and DMA-type peripheral devices.
Further, a need exists for FIFO buffers having means for direct (by-pass) communication with peripheral devices.